(a) Field of the Invention
The present invention relates to an interposer for a semiconductor device, more particularly, to an interposer adapted to realize a required fan-out structure between a semiconductor chip to be mounted thereon and a printed wiring board (packaging board) such as a mother board. The present invention also relates to a method of fabricating the interposer, and a semiconductor device using the same.
Such an interposer has a function of mounting a semiconductor chip thereon, and is therefore the same as a wiring board in terms of function and also referred to as a “package.”
(b) Description of the Related Art
A typical interposer has a semiconductor chip (typically a silicon (Si) chip) mounted thereon, and is mounted on a printed wiring board to constitute a semiconductor device. As a material constituting the interposer, various materials have been used. One example thereof is silicon (Si). The reason for using Si is that the same material as Si which is a material constituting the semiconductor chip to be mounted thereon is used (i.e., the coefficients of thermal expansion (CTEs) thereof are made approximately equal to each other) to prevent the occurrence of disadvantages such as a warp or a twist due to a difference in thermal shrinkage therebetween.
The interposer in which Si is used as its constituent material has an advantage in that the CTE thereof matches with that of the Si chip to be mounted thereon. In this case, from the viewpoint of CTE matching, it suffices that the size of the Si interposer is approximately the same as the chip size. However, the pitch of external connection terminals to be provided on the opposite surface to the side where the chip is to be mounted is larger than the pitch of terminals of the chip. Accordingly, the size of the interposer becomes larger than the chip size. In particular, where a chip having a large number of terminals is to be mounted, the size of the interposer becomes even larger. Namely, since the interposer is used to match the terminals of the Si chip to be mounted thereon and the terminals (external connection terminals) for connecting with a printed wiring board (i.e., to perform rewiring), the interposer exhibits a form in which an area for the external connection terminals is extended to the periphery of a chip mount area, i.e., a so-called “fan-out structure,” from the viewpoint of structure.
Moreover, when such a Si interposer is fabricated in a conventional process, a series of processings (formation of through holes, formation of an insulating layer in the through holes and on the wafer surface, formation of a seed layer or the like on the insulating layer, filling of the through holes with conductors by plating, formation of plated layers on both surfaces and formation of electrical paths between the both surfaces, formation of wiring patterns on the both surfaces, formation of protective films, and the like) are performed on a whole Si wafer, and then the Si wafer is diced into individual pieces (divided into individual pieces), each corresponding to one interposer. Further, external connection terminals are bonded thereto, as needed. Namely, the formation of wiring patterns is performed on the whole Si wafer.
Technologies relating to the above-described conventional technology include, for example, as described in Japanese unexamined Patent Publication (JPP) 2001-326305, an interposer for a semiconductor device in which a capacitor is provided between wiring patterns directly under a semiconductor chip to be mounted thereon.
As described above, conventional interposers have a “fan-out structure” in which an area occupied by external connection terminals is extended to the periphery of a chip mount area. Accordingly, there has been the following problem: where an interposer is fabricated using only silicon (Si), Si needs to be used even for an area which is essentially unnecessary from the viewpoint of CTE matching with a Si chip to be mounted thereon, i.e., an area extended to the periphery of the chip mount area; consequently, cost is increased.
Moreover, when an interposer is fabricated in a conventional process, processing is performed on the whole Si wafer until the Si wafer is finally divided into individual pieces. Accordingly, there has also been the problem in that it is technically difficult to form wiring patterns having required shapes on both surfaces of the Si wafer.